1. Field of the Invention
The present invention relates to a stacked semiconductor device, more particularly to a conductive pillar of a stacked semiconductor device which can decrease the delamination problem due to temperature changes.
2. Description of the Prior Art
The current trend in the electronic industry is to manufacture lighter, smaller, faster, multifunctional, and high-performance products at lower costs. To accomplish these objectives, multi-chip stacked package technology is used.
The multi-chip stacked package technology can reduce the overall volume and improve the electrical performance of the package and thus becomes a primary type of package in the industry. In the multi-chip stacked package, at least two semiconductor chips are mounted on a chip carrier and each of the chips is stacked on the chip carrier in a vertical manner.
However, the effect of differences in the coefficients of thermal expansion (CTE) between chips used in a semiconductor package can lead to detrimental defects as a result of temperature change.